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8085 Memory Interface

8085 Memory Interface

Terminology which are used.

  • Memory are made up of registers.
  • Each register consists of one storage location. 
  • Each location consists of an address.
  •  The number of storage locations from few hundreds to several mega or giga locations. 
  • The total number of memory storage is called memory capacity and measured in Bytes.
  •  Each register consists of storage element (FF, capacitor for semiconductor)
  •  A storage element is called cell.
  •  The data could be read from or written to memory.

Memory Structure and its requirements

  • As mentioned earlier, read/write memories consist of an array of registers, in which each register has unique address.
  • The size of the memory is N x M as shown below where N is the number of registers and M is the word length, in number of bits1




Summarizes capacity with address

Memory Capacity
Address lines required
1 k = 1024 memory locations
10
2 k = 2048 memory locations
11
4 k = 4096 memory locations
12
8 k = 8192 memory locations
13
16 k = 16384 memory locations
14
32k = 32768 memory locations
15
64k = 65536 memory locations
16


EPROM layout 

  • Shows the logic diagram of typical EPROM (Erasable Programmable Read-Only Memory) with 4096 (4k) registers 
  • It has 12 address lines (A0-A11), one chip select (CS), one Read control signal.
  • No WR signal




Basic Memory Interfacing with 8085 

  •  For interfacing memory devices to µp 8085, keep the following points in your mind:
  • µp 8085 can access 64KB memory since address bus is 16-bit.
  • Generally EPROM (or EPROMs) is used as a program memory and RAM (or RAMs) as data memory.
  • The capacity of program memory and data memory depends on the application. 
  • Is is not always necessary to select 1 EPROM and 1 RAM. We can have multiple EPROMs and multiple RAMs as per the rquirement of application 

Address Decoding techniques 

 There are two main techniques: 
       Absolute decoding/ Full Decoding
       Linear decoding / Partial Decoding 
  • Absolute Decoding: 
  •  All the higher address lines are decoded to select the memory chip, and the memory chip is selected only for the specified logic level on these high-order address, no other logic levels can select the chip.
  • The following figure shows the memory interface with absolute decoding.
  • This addressing technique is normally used in large memory systems. 

Absolute Decoding Technique 

Memory map 


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